1. Field of the Invention
This invention relates to mismatch noise shaping, in particular for digital-in-analog converters, subsequently referred to as DACs.
The invention relates especially to an efficient structure for "mismatch" noise shaping for DACs which have unequally weighted segments.
2. Description of the Prior Art
A simple DAC structure 1 is shown in FIG. 1. This seven segment DAC converts a 3 bit code 2(DAC input code [2:0]) into a corresponding analog signal 3 (Iout). The possible digital input 2 will range from 000 to 111 binary (decimal range 0-7). The segment selection logic 4 determines the DAC segments to be selected based on the digital input to the DAC, e.g. if the DAC input is 011 (binary) (decimal equivalent 3) then the segment selection logic will select 3 of the segments. This will produce an analog output of Iout equal to the sum of the currents of 3 individual segments.
In practice, there will be differences between the values of the individual segments. For example, each 1X segment value in FIG. 1 may have a nominal current output value of 1 mA. However, the individual segment values may range from 0.95 mA to 1 mA. The differences between segments is termed mismatch and the error arising from switching in and out segments having slightly different values is frequently referred to as mismatch noise.
The 5 bit DAC-subDAC structure illustrated in FIG. 2a consists of two DAC's 20, 21. The subDAC 21 illustrated functions as the DAC previously described and converts the 3 least significant bits (LSBs) of the DAC input code into an equivalent analog output signal (in this case a current). The main DAC converts the two most significant bits (MSBs) to an analog input. However, the weighting of each segment in the main DAC is eight times that of the subDAC (as the units of the DAC segments are effectively eighths, whereas the units of the subDAC are ones).
This particular arrangement will have three sources of mismatch noise:
1. The mismatch error arising between segments in the subDAC. PA1 2. The mismatch error arising between segments in the main DAC. PA1 3. The mismatch error arising from differences in the average values of main DAC segments and the equivalent number of subDAC segments, (e.g. if the average value for a segment in the main DAC was 8 mA and in the subDAC 1.1 mA then mismatch error would be 8.times.1.1-8=0.8 mA). PA1 a plurality of selectable segments, at least two of which have a first weighting factor and two of which have a second weighting factor, the segments when selected being connected to a reference signal, such that the output for a segment, when selected, is proportional to the weighting factor of that segment, the number of segments having the second weighting factor being equal to at least twice the ratio of the first and second weighting factors less one, PA1 selection means for selecting segments based on the digital input, PA1 summing means for adding the output from each selected segment to produce an analog output, PA1 monitoring means for monitoring the number of times segments having the second weighting factor are selected in a given monitoring period and for generating a correction signal when this number diverges from a specified target value, and PA1 correcting means responsive to said correction signal of the monitoring means to adjust the number of segments selected having the first weighting factor and to adjust the number of segments selected having the second weighting factor by an equivalent amount. PA1 a plurality of selectable segments, at least two of which have a first weighting factor and at least two of which have a second weighting factor, the segments when selected being connected to a reference signal, with the output for each segment, when selected, being proportional to the weighting factor of that segment, and the number of segments having the second weighting factor being equal to at least twice the ratio of the first and second weighting factors less one, PA1 selection means for selecting segments based on the digital input, PA1 summing means for adding the output from each selected segment to produce an analog output, PA1 monitoring means for monitoring the number of times segments having the second weighting factor are selected in a given monitoring period and for generating a correction signal when this number drops below a specified target selection value, PA1 borrow means responsive to said correction signal of the monitoring means to reduce the number of segments selected having the first weighting factor and increase the number of segments selected having the second weighting factor. PA1 two R-2R networks in parallel, each R-2R network having a series of selectable switches, each switch having a different binary weighting, PA1 subDAC control means adapted to select said selectable switches in response to the digital input code, and PA1 summing means adapted to sum the resulting output of each selectable switch and the main DAC to produce an analog output.
The R-2R DAC shown in FIG. 2b can be considered as a special case of the DAC-Sub DAC structure, in that it comprises a series of subDACs, each having different weightings, each subDAC having only one segment. In this case, the mismatch error will be restricted to that of the third class described above.
Techniques for "noise-shaping" the errors which arise from mismatch in the analog components of over-sampled data converters have recently been presented by Schreier, R. and Zhang, B: "Noise-shaped multibit D/A converter employing unit segments", Electron. Lett., 31, 1995, pp. 1712-1713, and Baird, R. T. and Fiez, T. S.: "Linearity enhancement of multibit Sigma Delta converters using data weighted averaging", IEEE Trans. Circ. & Sys. II, 1995, pp. 753-762.
The techniques have been applied to fully segmented DACs such as that of FIG. 1. The DAC output is set by selecting a number of segments to be connected to a reference voltage. The mapping of input code to selected segments is not unique. For instance, if the input code requires that two segments be selected, then any two segments can be selected. The mismatch noise shapers work by dynamically changing the mapping of input codes to segments, so that each segment's usage, within the passband of the converter, reflects the input signal. This ensures that mismatch error contributions from the individual components reflect the input signal and so appear as gain errors.
A very elegant method is to use the segments in a strict cyclic sequence, as proposed by Baird et al (above), which ensures that, on average over time, each element's usage is proportional to the input signal, with a residual noise component which is first order shaped. The use of a tree structure for the element selection algorithm is described by Galton I.: "A hardware efficient noise-shaping D/A converter", Proc. IEEE International Symposium On Circuits And Systems, May 1996. The use of such a tree structure means in addition that the digital logic overhead can be kept small, as also described by Keady A. and Lyden C.: "Tree structure for mismatch noise-shaping multibit DAC", Electron. Lett., 33, 1997, pp. 1431-1432.
Fully segmented N-bit DACs require 2.sup.N elements, and so are quite large if N is 8 or more. For such higher resolutions, it is common to use a DAC-subDAC structure, as shown in FIG. 2a, or more classically an R-2R DAC, shown in FIG. 2b. These DAC structures are efficient, as they require far fewer than 2.sup.N elements. However, it is not straightforward to apply mismatch noise shaping, as the elements have different weightings and so are not fully interchangeable.
It is an object of the invention to provide a technique for mismatch noise shaping DACs having a DAC-subDAC structure.
It is further an object of the invention to provide a technique for mismatch noise shaping R-2R type DAC's by treating them as a particular type of DAC-subDAC structure.